Un_Known Posted July 1, 2019 Posted July 1, 2019 Can somebody explain following post indexing example from ARM instruction set LDR r0, [r1] ,r2, lsl#3
Un_Known Posted July 1, 2019 Author Posted July 1, 2019 3 hours ago, Un_Known said: Can somebody explain following post indexing example from ARM instruction set LDR r0, [r1] ,r2, lsl#3 @Enyby @saiaapiz
saiaapiz Posted July 1, 2019 Posted July 1, 2019 Read this, there also answer for question about PC + 8. https://azeria-labs.com/memory-instructions-load-and-store-part-4/
Moderators NoFear Posted July 1, 2019 Moderators Posted July 1, 2019 I feel the arm instruction set you have isn't correct. Give original hex from that instruction set. Also, link given above is good. And here http://www.keil.com/support/man/docs/armasm/armasm_dom1361289850039.htm
Un_Known Posted July 1, 2019 Author Posted July 1, 2019 1 hour ago, NoFear said: I feel the arm instruction set you have isn't correct. Give original hex from that instruction set. Also, link given above is good. And here http://www.keil.com/support/man/docs/armasm/armasm_dom1361289850039.htm No.Instruction is absolutely correct ! Here ARM v7 Hex for this instruction is : 820191E6 and equivalent ARM v7 Thumb instruction for this is : LSLS R2, R0, #6 B #0xFFFFFD28 @NoFear
Moderators NoFear Posted July 1, 2019 Moderators Posted July 1, 2019 1 hour ago, Un_Known said: No.Instruction is absolutely correct ! Here ARM v7 Hex for this instruction is : 820191E6 and equivalent ARM v7 Thumb instruction for this is : LSLS R2, R0, #6 B #0xFFFFFD28 @NoFear Site I use wasn't putting it back to hex for whatever reason. Odd.... Edit: it's not ARMV7. that's why. It's thumb. Need to pick the correct arm assembly. It's not both. It's either v7, v7 thumb or armv8/64.
Un_Known Posted July 2, 2019 Author Posted July 2, 2019 5 hours ago, NoFear said: Site I use wasn't putting it back to hex for whatever reason. Odd.... Edit: it's not ARMV7. that's why. It's thumb. Need to pick the correct arm assembly. It's not both. It's either v7, v7 thumb or armv8/64. No! I think take a look. The instruction i shared was v7 ARM and it's legitimate one but i want to understand this particular example only because i know the concept of post indexing addressing but this particaular example is giving me hard time! I read guide and references but couldn't find clue to it! This is bit difficult than others hope somebody would help!
Un_Known Posted July 2, 2019 Author Posted July 2, 2019 Sorry bit of confusion was there correction LDR r2,[r1],r0,lsl#3 = 802191E6 LDR R0,[R1],R2,LSL#3 = 820191E6 just want to know what is happening in this particular example
Moderators NoFear Posted July 2, 2019 Moderators Posted July 2, 2019 45 minutes ago, Un_Known said: Sorry bit of confusion was there correction LDR r2,[r1],r0,lsl#3 = 802191E6 LDR R0,[R1],R2,LSL#3 = 820191E6 just want to know what is happening in this particular example I'm thinking it's Thumb.... You are getting a hex result, but it's saying conversion failed. The 802.... Hex MOVS R1, #0x80 B #0xFFFFFD28 Is moving 128 to R1 Your 820820191E6 hex LSLS R2, R0, #6 B #0xFFFFFD28 Quote 16-bit instructions The following forms of this instruction are available in Thumb code, and are 16-bit instructions: LSLS Rd, Rm, #sh Rd and Rm must both be Lo registers. This form can only be used outside an IT block Edit: LSL Logical Shift Left. This instruction is a preferred synonym for MOV instructions with shifted register operands.
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Can somebody explain following post indexing example from ARM
instruction set
LDR r0, [r1] ,r2, lsl#3
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